With the rapid development of semiconductor manufacturing technology, semiconductor chip is making progress in the direction of highly integration, in order to achieve much faster operating speed and more data storage content and more performance. The higher the integration level of semiconductor chip is, the smaller the critical dimension (CD) of semiconductor chip is.
Along with the critical dimension of semiconductor chip gradually becomes small, the influence on the operating speed which RC delay makes is becoming more and more obvious. How to reduce RC delay is one of the hot issues being studied by the technical personnel in the field. One of the methods to solve RC delay is to decrease parasitic capacitance between metal lines.
A plurality of methods to decrease parasitic capacitance have been developed in prior art, for example, to fill multiaperture low-K dielectric material between metal lines. However, multiaperture material is fragile which cause the worse reliability for the semiconductor device using multiaperture low-K dielectric material.
Another method has been developed to form air gap between metal lines so as to decrease dielectric constant and then decrease parasitic capacitance, for example, employing self-organizing organic polymer to form air gap. But aforesaid method is harder to compatible with the existing processing method of semiconductor, and the manufacturing process is more complex.